1.15. Running Make multiple times

As explained in Section 1.11.3: Anatomy of the Makefile - targets and rules, , Makefiles are target based. We try to give a target, and it’s dependencies / rules.

 1TARGETS=greeting_en greeting_fr greeting_es
 2
 3all: $(TARGETS)
 4CFLAGS := -Wall
 5
 6$(TARGETS):
 7	gcc main.c $@.c $(CFLAGS) -o $@
 8
 9clean:
10	-@rm $(TARGETS)
11
12run:
13	$(foreach target,$(TARGETS), ./$(target);)

Let’s just compile it once, as we have done earlier.

make all

The output would also be as seen earlier:

gcc main.c greeting_en.c -Wall -o greeting_en
gcc main.c greeting_fr.c -Wall -o greeting_fr
gcc main.c greeting_es.c -Wall -o greeting_es

Now, let’s run the makefile once more.

make all

When we run make 2nd time, the output is as below.:

make: Nothing to be done for 'all'.

Note

You can see here that make knows that nothing new is needed because the target already exists.