1.13. Makefile with Variables¶
The approach in previous section (Makefile with more default convention) looks nice, but we can as well try to simplify the Makefile with some variables.
TARGETS=greeting_en greeting_fr greeting_es all: $(TARGETS) $(TARGETS): gcc main.c $@.c -Wall -o $@ clean: rm $(TARGETS) run: $(foreach target,$(TARGETS), ./$(target);)
To compile that file with GCC, the command would be.
When the above command completes successfully, the compilation output would be:
gcc main.c greeting_en.c -Wall -o greeting_en gcc main.c greeting_fr.c -Wall -o greeting_fr gcc main.c greeting_es.c -Wall -o greeting_es
To execute the binary generated from the source file, the command would be as shown below.
If everything went fine, the output would be:
./greeting_en; ./greeting_fr; ./greeting_es; Hello World! Bonjour le monde! Hola Mundo!